This invention relates generally to charge-coupled semiconductor devices and, more particularly, to a charge transfer device (CTD) operated by a single clock line. In the ensuing description the uniphase charge transfer device of the present invention is referred to as a charge-coupled device (CCD), although CCD's are generally defined as charge transfer devices in which virtually all of the charge is transferred forward from one charge storage region to the next (complete charge transfer mode).
A known type of single-phase CCD is described in "Two-Phase Charge-Coupled Devices with Overlapping Polysilicon and Aluminum Gates," RCA Review, Vol. 34, March, 1973. In this article it is stated that a two-phase charge-coupled device can be operated with one of the phases biased to a DC voltage which is halfway between the minimum and the maximum voltage applied to the other phase. A similar single-phase CCD is described in "A CCD Line Adjustable Random-Access Memory (LARAM)", IEEE Journal of Solid State Circuits, Vol. SC-10, No. 5, October, 1975, wherein is disclosed a buried channel CCD in which the buried channel contains a series of barrier implants. As with the CCD described in the first publication, alternate electrodes are held at a fixed DC potential approximately halfway between the potential extremes of the clocked electrodes. The aforementioned types of single-phase CCD's do not in actuality dispense with the necessity for two separate clock lines, and thus such devices are subject to attendant problems of phase synchronization and limitations on device layout and density.
The RCA Review article also states that a uniphase CCD which requires only a single set of clocked gates can be constructed by using a fixed charge in the channel oxide as a built-in bias to achieve the required potential profile. U.S. Pat. No. 3,796,933 describes a variation of this type of single-phase CCD, wherein the semiconductor substrate contains an impurity gradient from one end of the device to the other. The impurity gradient, together with the single-phase clocking, creates the unidirectionality of charge movement through the device. The CCD disclosed in U.S. Pat. No. 3,796,933 necessarily has a limitation on the number of consecutive storage regions, due to the requirement for a graduated impurity region in the substrate. Furthermore, the construction of CCD's having graduated impurity regions is rather complicated. In addition such devices contain unsealed channels which cause well known deleterious effects and instabilities.